The three will invite other players in the industry in a bid to develop chip manufacturing technologies that can more than halve the semiconductor line widths to nearly 10 nanometers by 2016. A nanometer is unit of length in the metric system that equals one-billionth of a meter.
According to the report, the Ministry of Economy, Trade and Industry in Japan will put up 5 billion yen toward an initial 10 billion yen in funds for R&D efforts, with the other half coming from members of the consortium itself.
Samsung and Toshiba are the world's largest and second largest makers of NAND-type memory respectively, and will use any resulting manufacturing technology to produce 10-nanometer class NAND flash memory chips, while Intel will use the technology for a new generation of powerful microprocessors.
Written by: James Delahunty @ 29 Oct 2010 18:20
